--
-- VHDL Architecture infrarood_lib.edge_detector.v
--
-- Created:
--          by - John.UNKNOWN (EPOX)
--          at - 16:12:15 03/23/2007
--
-- using Mentor Graphics HDL Designer(TM) 2005.2 (Build 37)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY s_edge_detector IS
   GENERIC( 
      rv : std_logic := '1'
   );
   PORT( 
      i        : IN     STD_LOGIC;
      clk      : IN     STD_LOGIC;
      ena      : IN     STD_LOGIC  := '1';
      rst      : IN     STD_LOGIC;
      pos_edge : OUT    STD_LOGIC;
      neg_edge : OUT    STD_LOGIC;
      edge     : OUT    STD_LOGIC;
      q0       : BUFFER STD_LOGIC
   );

-- Declarations

END s_edge_detector ;


ARCHITECTURE v OF s_edge_detector IS



  SIGNAL q2 : STD_LOGIC;
  SIGNAL q1 : STD_LOGIC;
  

BEGIN
  
  
  PROCESS(rst, clk)
    BEGIN
      IF rst = '1' THEN
        q2 <= rv;
        q1 <= rv;
        q0 <= rv;
      ELSIF RISING_EDGE(clk) THEN
        
        IF ena = '1' THEN
          q2 <= i;
          q1 <= q2;
        END IF;
        q0 <= q1;
        
      END IF;
    END PROCESS;
  
  
    
    
    pos_edge <= q1 AND NOT q0;
    neg_edge <= NOT q1 AND q0;
    edge     <= q1 XOR q0;
    

    

    
  END ARCHITECTURE v;

